Conventional semiconductor fabrication processes have reduced device geometries to facilitate the fabrication of relatively dense memory cells. Memories having higher densities, however, are vulnerable to increased defect rates (e.g., defects per unit area). T0 salvage memory that otherwise would be lost due to defects, memory designers usually include extra memory to replace defective memory.
A conventional approach to salvaging memory divides a memory array into multiple, equal-sized areas in which each plane in a grouping is a separate, isolated collection of memory cells. A FLASH memory array, for example, can be partitioned into four equal areas. By partitioning memory in this manner, a memory is less susceptible to fatal defects that otherwise render the entire memory (e.g., the aggregate of all groupings) inoperative. T0 illustrate, consider that a defect in an un-partitioned memory causes an entire area to fail. As such, the entire memory array is unusable. But if the memory is partitioned, the defect will at most affect only the grouping in which the defect(s) resides. This allows the memory to remain usable, albeit with less memory capacity. T0 recover lost memory, some memories traditionally include extra columns in each grouping to replace a limited number of columns having defects. These extra columns are typically selected by programming bits stored in non-volatile registers to indicate which one of a number of substitute columns will be used to replace a defective column. Therefore, each grouping is usually associated with a dedicated set of non-volatile registers. Further, each grouping usually includes an extra decoder to uniquely select each of the extra columns.
While this approach is functional, it has drawbacks. First, extra columns, non-volatile registers, and extra decoders, if used, collectively consume amounts of surface area in traditional memory architectures. This, in turn, increases the die size (e.g., in the X and Y dimensions of the die). Second, memory designers are typically faced with deciding how many extra memory columns to add to each grouping, especially since memory fabrication processes can randomly cause any number of unforeseen defects. If a memory designer adds too many extra columns, then any unused memory that does not remedy a defect will unnecessarily increase the die size. But if the memory designer adds too few extra columns, then the memory array cannot support its intended memory capacity, which decreases the yield of good memories. Third, conventional column replacement techniques, as described above, do not usually adapt to the different defects rates that each grouping might experience. For example, consider that each of eight groupings includes five extra columns to replace five defective columns, if necessary. Next, consider that a fabrication process introduces defects in each memory as follows: one of the eight groupings has six defective columns while the other groupings have two defective columns. As is common, the extra columns in the other groupings (e.g., the ones with two defective columns) cannot be used to replace the sixth defective column, and, thus, the sixth column renders its grouping inoperative. Fourth, accessing the extra columns using conventional column replacement techniques can ordinarily have longer access times than accessing a main array, especially if the detection of defects and implementation of the extra columns are performed, for example, serially.
There are continuing efforts to improve technology for salvaging memory that include defects.
Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the described drawings are not necessarily drawn to scale.